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Hi everybody, I am experiencing a strange behavior on my design. The USB JTAG programmer detects the two devices, reads the IDs, programs them correctly, and the contents are verified.

Evrything is perfect. But when I power up the FPGA fails to load its config from the prom device. Safe Place To Download Anime. After reading the other posts, I found that Bob Elkind (thanks Bob) suggested to connect a switch for force reloading the config. It doesn't work.

I checked with a scope and found that the CCLK signal is generated, so the init sequence takes place. I have been using the same schematics in two previous designs and it works. Any clever or most stupid suggestion will be welcome at this stage!! Thanks to all Jean Louis. The only thing obvious is that you have some pull-up resistors going to 2.5V while the XCF02S is running with Vcc of 3.3V. You may want to check that these signals meet the Vih requirements of the PlatformFlash.

Are you able to directly program the FPGA via JTAG? If not I suspect there may be a problem other than just the way the flash is hooked up. Also your schematic shows one flash device but the text says 'Piggyback.' Are you actually using two XCF02S devices?

If so how are they chained together? Gabor, first thank you for replying. The pull-up resistors going to 2.5V are explicitely described in the Xilinx app note DS312, page 72, and the piggyback is a very small PCB board that plugs into the mother board for easy PROM swapping when required on a customer site. I am using only one XCF02S device, and I am sure of the connections of this piggyback board (already used twice in previous FPGA designs) (see pic). And yes, I can program the FPGA via JTAG.

Strange behavior. Honeywell Dial Set Chronotherm Manual Woodworkers. THANKS again, I appreciate. This is an interesting post. Gucci Serial Number Check Cap.

So I took at look at DS312 (July 19, 2013), figure 51, page 71 that the OP referenced. This figure shows a 2.5v JTAG interface, and not a 3.3v JTAG interface. The figure shows the PROM's VCCJ at 2.5v. It shows the 3E's VCC0_2 at 3.3v. Because the PROM's VCCJ supplies power to the PROM's TDO driver and to the TCK, TDI, and TMS input buffers, it would appear that in the OP's circuit that those pins do not meet VIH for his PROM. But then, I took a look at UG332 (Oct 26, 2009), figure 3-1, page 80, and it looks similar to the OP's circuit, with the exception that the FPGA is first in the chain.